Model Technology Model Sim EE Manual de usuario

Modelsim SE Tutorial byAni [email protected] DepartmentIndian Institute of Technology, Bombay

Getting Started with Projectsthe four basic steps to working with a project.• Step 1 — Creating a New Project This creates a .mpf file and a worki

Step 1 — Creating a New Projecta. Select File > New > Project (Main window) from the menu bar. This opens the Create Project dialog where y

e. you can also Click the Browse button for the Project Location field to select an existing directory where the project file will be stored.f. Leave

Step 2 -Adding items to the project•The following window pops up• Create New File — Create a new VHDL, Verilog or text file using the Source editor.•

•Create new file• Press the Create new file option• You can also create a new project file by selecting Project > Add to Project > New File (the

•Add Existing File•You can add an existing file to the project by selecting Project > Add to Project > Existing•File or by right-clicking in the

•Step 3 — Compiling the Files•The question marks in the Status column in the Project tab denote either the files haven’t been compiled into the projec

•ModelSim compiles all the files and changes the symbol in the Status column to a green check mark. A check mark means the compile succeeded.• If com

•i intent to demonstrate how to use a self defined resource library the concept of which was introduced earlier•Consider I had earlier created a pro

•now let us move to the current working directory c:/Xilinx/bin/tutorial•Now I make a new resource library by with the graphic interface, select File

CONTENTS1>What problem Modelsim addresses ?2>Tool Structure and Flow3>Design Libraries 4>Projects Step 1 — Creating a New Project

• Since this is library is user defined we need to map this logical library “mylib” to a path name of the library .Next we need to map the empty libr

• The same mapping can be done through the modelsim command line using the vmap command vmap <logical_name> <directory_pathname> i

•I also add a package called “mypackage” to the current project :•The package basically has a function called “myand” which basically performs a “AND”

•Here is the adder2.vhd that makes use of the resource library “mylib” and the package “mypackage”•The file uses the myxor entity provided by the “myl

•Step 4 — Simulating a Design•To simulate a design• select Simulate > Start Simulation from the menus to open the Start Simulation dialog• Select

4.1>Running the simulation Now you will open the Wave window, add signals to it, then run the simulation.1. Open the Wave debugging window. a.

• We need to give the input vector to the signals.

• We can the input either through a Test bench or by Forcing the values for the input signals• We view the signals from View > signals .•The inputs

3. Run the simulation.b. Click the Run icon in the Main or Wave window toolbar.The simulation runs for 100 ns (the default simulation length) and wave

4.2>Using Break points for debug..•Modelsim provides us the facility of running the simulation till a particular point in the code called a “break

1>What problem Modelsim addresses ?•ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, and mixed language

• For example here I click the test1 entity and the source window opens the adder2.vhd •To set a breakpoint just take your mouse pointer to the line n

• after creating the break point we can run the simulation else if we have already run the simulation earlier we can use the restart simulation option

When a breakpoint is reached, typically you would want to know one or more signal values. You have several options for checking values:• look at

5>A quick example with Verilog•The procedure remains the same for verilog design as well .•You can use the same project for VHDL or Verilog design

•The code after successful compilation :the simulation is absolutely identical to the previous slides with a vhdl code

6>MIXED VHDL/VERILOG SIMULATION • Modelsim also provides the user the option to compile and simulate designs units which instantiates design units

Heres the verilog file register.v•Here is the top most design unit serialbitadder which uses the registerv module.

• Compiling the files : However, in a mixed VHDL/Verilog design, the Verilog files must be compiled before the VHDL files.. •In general the verilog fi

• Notice the hierarchical mixture of VHDL and Verilog in the design. VHDL levels are indicated by a square “prefix”, while Verilog levels are indicate

7>Command line options :• Modelsim also provides the user with command line options some of which are shown below :

•Modelsim can be invoked in any of the VLSI lab PCs by typing “vsim” at the command prompt .

8>Conclusion and Further learning•This tutorial is more than sufficient for beginners to start simulating any HDL description .• The most important

2>Tool Structure and Flow

3>Design Libraries• VHDL , Verilog designs are associated with libraries, which are objects that contain compiled design units.•A design library is

•ModelSim uses libraries in two ways: •1) as a local working library that contains the compiled version of your design (ie VHDL , Verilog code etc)

•The Library Named "work“• it is predefined in the compiler and need not be declared explicitly (i.e. library work). It is also the library name

4>Projects•when you create a project in a working directory , a work library gets automatically created for that particular working directory or